1. Field of the Invention
The present invention relates to a semiconductor memory device such as SDRAM (Synchronous Dynamic Random Access Memory); and more particularly to a semiconductor memory device such as SDRAM of a posted CAS specification that allows free selection of the time interval from the input of an ACTV command, which is a command instructing the selection of a row address, to the input of a READ command, which is a command instructing the selection of a column address; and to a method of controlling the reading of data from this type of semiconductor memory device.
2. Description of the Related Art
With the increase in CPU speed in recent years has come the demand for DRAM having the capability to read and write data at higher speeds. SDRAM, in which operations are carried out at higher speeds by operating in synchronization with an external clock signal, has come into wide use to achieve these higher data transfer rates. Even higher data transfer rates are achieved through the use of DDR (Double-Data-Rate) SDRAM, in which higher data transfer speeds are realized by transferring data at both the falling and rising edges of a clock signal.
In addition, the DDR-II specification, which is a method for handling the higher speeds of DDR, is now under investigation to achieve a further increase in speed. This DDR-II standard allows a lower power-supply voltage and a clock frequency of 400 MHz or more. We now refer to FIG. 1, which is a block diagram showing the simplified structure of such an SDRAM. The SDRAM shown in this figure is provided with: clock generator 10, control circuit 11, address buffer 12, row decoder 13, column decoder 14, memory cell array 15 that is constituted by a plurality of memory cells provided at each intersection of word lines and bit lines, and data input/output buffer 16.
Clock generator 10 receives as input differential clock inputs CK, /CK, and CKE (Clock Enable), generates clock signal CLK, and outputs this clock signal to each circuit.
Control circuit 11 receives as input /CAS (Column Address Strobe), /RAS (Row Address Strobe), /WE (Write Enable), and /CS (Chip Select); and controls the writing and reading of data to each memory cell of memory cell array 15. Here, as shown in FIG. 2, control circuit 11 operates as if an ACTV command, which is a command instructing the selection of row address, has been received when /CS is L, /RA is L, /CAS is H, and /WE is H; operates as if a READ command, which is a command instructing the selection of a column address, has been received when /CS is L, /RAS is H, /CAS is L, and /WE is H; and operates as if a PRE command, which is a command instructing precharging, when /CS is L, /RAS is L, /CAS is H, and /WE is L.
More specifically, upon receiving an ACTV command, control circuit 11 outputs address control signal 201 to address buffer 12 and then activates control signal φ1 for controlling row decoder 13. Upon receiving a READ command, control circuit 11 outputs address control signal 202 to address buffer 12 and then activates both control signal φ2 for controlling column decoder 14 and control signals φ3 for controlling data input/output buffer 16. Then, after receiving a PRE command, control circuit 11 inactivates both address control signal 201 and control signal φ1 to row decoder 13.
Address buffer 12 receives bank selection signal BA and address signal A, and when address control signal 201 becomes active, address buffer 12 outputs row address AX within address signal A to row decoder 13, and when address control signal 202 becomes active, outputs column address AY within address signal A to column decoder 14.
SDRAM is actually constituted by a plurality of banks, and address buffer 12 outputs row address AX and column address AY only when a received bank selection signal BA selects the relevant memory cell array 15, but for the sake of simplification in the following explanation, bank selection signal BA will be assumed to select memory cell array 15.
When row decoder 13 receives row address AX from address buffer 12 and control signal φ1 becomes active, row decoder 13 both activates the word line that corresponds to received row address AX of the plurality of word lines WL and activates sense amplifier control signal SAC. When column decoder 14 receives column address AY from address buffer 12 and control signal φ2 becomes active, column decoder 14 activates the column selection signal that corresponds to received column address AY of the plurality of column selection signals YS. When control signal φ3 becomes active, data input/output buffer 16 outputs the data from memory cell array 15 as output data DQ.
The structure of memory cell array 15 in FIG. 1 is shown in FIG. 3. In FIG. 3, memory cell array 15 is described as an array that is constituted by m×n memory cells (MC). As shown in FIG. 3, memory cell array 15 is made up of m columns, each column being provided with n memory cells. Each column is provided with a respective precharge circuit (PRE), sense amplifier, and Y-switch circuit. The precharge circuit that is provided in each column is controlled by precharge signal PDL from row decoder 13. The sense amplifier that is provided for each column is similarly controlled by sense amplifier control signal SAC from row decoder 13. The Y-switch circuits that are provided in each column are independently controlled by column selection signals YS1-YSm from column decoder 14, and only the Y-switch circuit of a column that is indicated by a column address AY is activated. Finally, in FIG. 1, word lines WL1-WLn are simply indicated as WL and column selection signals YS1-YSm are simply indicated as YS.
We next refer to the timing chart of FIG. 4 to describe the operations when reading data from the SDRAM shown in FIG. 1.
First, the input of an ACTV command, which is a command instructing the selection of a row address, to control circuit 11 causes address control signal 201 to be output from control circuit 11 and a row address AX to be output from address buffer 12 to row decoder 13. The activation of control signal φ1 by control circuit 11 then causes row decoder 13 to both deactivate precharge signal PDL and select the word line that corresponds to the received row address AX of word lines WL1-WLn. Row decoder 13 then activates sense amplifier control signal SAC for activating the sense amplifiers of memory cell array 15, whereby the word lines WL that contain memory cells for which data are to be read are activated, and data are read to bit lines BL and /BL and the bit lines amplified. Of the area of memory cell array 15, the area that is activated by the processes up to this point is shown in FIG. 5. In FIG. 5, a case is shown in which word line WL3 has been activated by row decoder 13, and the activated area is indicated by diagonal lines.
A READ command instructing the selection of a column address is received as input from external system two clocks, i.e., tRCD, after the ACTV command has been received, whereupon control circuit 11 activates both address control signal 202 and control signal φ2. The activation of these signals causes column address AY to be applied as input from address buffer 12 to column decoder 14, whereby only column selection signals that are indicated by the column address AY of column selection signals YS1-YSm are activated, and the memory cells that are to be read are selected. The activation of control signal φ3 then causes the data from the selected memory cells to be output from data input/output buffer 16 as data DQ.
When precharge command PRE is subsequently received as input, control circuit 11 deactivates control signal φ1, whereby row decoder 13 deactivates the word lines WL that were active, deactivates sense amplifier control signal SAC, and activates precharge signal PDL. Bit lines BL and /BL are reset by these operations in preparation for the next data reading of memory cells.
In an SDRAM of this type, a certain amount of time is required from the time that the word lines WL are selected by row decoder 13, the sense amplifier control signal SAC becomes active, and the sense amplifier begins to operate until the time that the amplification of the bit lines ends. As a result, the selection of bit lines by column selection signals YS1-YSm must wait until the end of the amplification of the bit lines. More specifically, when applying a READ command after applying an ACTV command as input in an SDRAM of the prior art, the passage of a stipulated time tRCD must be guaranteed in the external system that controls the reading and writing of data. In other words, tRCD is stipulated for guaranteeing time for the amplification of bit lines BL and /BL to end after the input of an ACTV command. The timing chart shown in FIG. 4 shows a case in which two clocks are stipulated as this time tRCD. This type of constraint necessitates extra work in the external system control.
The adoption of a posted CAS standard in the above-described DDR-II SDRAM is being investigated for the purpose of eliminating this constraint on the external system and facilitating control. This posted CAS standard is free from the tRCD constraint, i.e., that a number of clocks that must be guaranteed from the input of an ACTV command until the input of a READ command and allows the external system to continuously apply an ACTV command and READ command.
We next refer to the timing chart of FIG. 6 of an SDRAM in which this type of posted CAS standard has been adopted. The timing chart shown in FIG. 6 differs from the timing chart of FIG. 4 in that a READ command is applied as input immediately after the input of an ACTV command, and in that the input of the READ command to control circuit 11 causes column address AY to be output to column decoder 14 more quickly than in the prior art.
In this posted CAS SDRAM, control circuit 11 controls the timing of the output of control signal φ2 for controlling the timing at which column decoder 14 outputs column selection signal YS, whereby the output of the data of bit lines to data input/output buffer 16 before the completion of amplification of the bit lines is prevented for cases in which a READ command is applied as input to control circuit 11 before the passage of tRCD after the input of an ACTV command.
Thus, in this type of posted CAS SDRAM, control circuit 11 stores tRCD in advance such that even when a column address is selected before the passage of tRCD, control circuit 11 exercises control in place of the external system over the timing of actual execution of a READ command that was controlled by the external system of the prior art.
As a result, in this posted CAS SDRAM, an external system can execute a READ command without having to make allowances for tRCD. In other words, the external system can execute a READ command immediately after, i.e., one clock after, executing an ACTV command, whereby the control for reading data can be facilitated in the external system that controls data reading.
In this case, the number of cycles following a READ command until tRCD is referred to as AL (Additive Latency). In the example shown in FIG. 6, AL=1. In this posted CAS SDRAM, however, a column address AY must be latched for a period of time that is determined by AL.
As described in the foregoing explanation, the use of DDR-II SDRAM enables the realization of a semiconductor memory device having a higher data transfer rate. Further, an SDRAM that employs the posted CAS standard increases the freedom of control in the external system and therefore can realize a semiconductor memory device that facilitates control by an external system. Even when the posted CAS standard is used, however, the number of cycles that are required from the input of an ACTV command until the output of data DQ is tRCD+CL (CAS Latency), and therefore is identical to an SDRAM of the prior art that does not employ the posted CAS standard.
In other words, despite the use of posted CAS SDRAM in the semiconductor memory device of the above-described prior art, the time from the input of an ACTV command until the actual output of data is no different from a case in which the posted CAS standard is not used, and the problem remains that tRCD constituted a rate-determining condition, and an increase in the data transfer rate could not be achieved.